Features
- 128-Pin E-pad TQFP
- State machine implementation without external memory (RAM, flash) requirement
- Complies with IEEE 802.11a/b/g standards
- Supports descriptor-based buffer management
- Integrated Wireless LAN MAC and Direct Sequence Spread Spectrum/OFDM Baseband Processor in one chip
- Enhanced signal detector, adaptive frequency domain equalizer, and soft-decision Viterbi decoder to alleviate severe multipath effects
- Processing Gain compliant with FCC
- On-Chip A/D and D/A converters for I/Q Data, AGC, and Adaptive Power Control
- Targets Multipath Delay Spreads of 125ns at 11Mbps
- Supports both transmit and receive Antenna Diversity
- Data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36, 48, and 54Mbps. Turbo mode supports 72Mbps
- Supports CardBus. The CIS can be stored in a 93C56
- Supports 40MHz OSC as the internal clock source. The frequency deviation of OSC must be within 25 PPM on IEEE 802.11g and 20 PPM on IEEE 802.11a
- Complies with PC97, PC98, PC99, and PC2001 standards
- PCI local bus network interface controller
- Complies with PCI Revision 2.2 and MiniPCI Revision 1.0
- PCI power management Revision 1.1
- PC Card Revision 8.2
- Supports PCI clock 20MHz~36MHz
- Supports PCI target fast back-to-back transactions
- Supports Memory Read Line, Memory Read Multiple, Memory Write and Invalidate
- Provides PCI bus master data transfers and PCI memory space or I/O space mapped data transfers of the RTL8185L’s operational registers
- Supports PCI VPD (Vital Product Data)
- Supports ACPI, PCI power management
- Supports Wake-On-LAN (WOL) function and remote wake-up (Magic Packet and Microsoft® wake-up frame)
- Supports 4 WOL signals (active high, active low, positive pulse, and negative pulse)
- Supports auxiliary power auto-detect, and sets the related capability of power management registers in PCI configuration space
- IEEE 802.11g protection mechanisms for both RTS/CTS and CTS-to-self
- Burst-mode support for dramatically enhanced throughput
- Supports jumbo frames
- DSSS with DBPSK and DQPSK, CCK modulations and demodulations supported with long and short preamble
- OFDM with BPSK, QPSK, 16QAM and 64QAM modulations and demodulations supported with rate compatible punctured convolutional coding with coding rate of 1/2, 2/3, and 3/4
- Efficient IQ-imbalance calibration, DC offset, phase noise, frequency offset and timing offset compensation reduce analog front-end impairments
- Selectable digital transmit and receiver FIR filters provided to meet transmit spectrum mask requirements and to reject adjacent channel interference
- Programmable scaling both in transmitter and receiver to trade quantization noise against the increased probability of clipping
- Fast receiver Automatic Gain Control (AGC) & antenna diversity functions
- Adaptive transmit power control function
- Hardware-based IEEE 802.11i encryption/decryption engine, including 64-bit/128-bit WEP, TKIP, and AES
- Programmable PCI burst size for both read and write commands
- Supports a 32-bit general-purpose timer with the external PCI clock as clock source
- Contains two large independent transmit and receive FIFO buffers
- Advanced power saving mode when the LAN and wakeup function are not used
- Uses 93C46 (64*16-bit EEPROM) or 93C56 (128*16-bit EEPROM) to store resource configuration, ID parameter, and VPD data
- LED pins for various network activity indications
- Two GPIO pins supported
- Supports digital loopback capability on both ports
- Flexible RF transceiver interface for different RF transceiver applications
- Scatter and gather operation
- 3.3V and 1.8V power supplies required
- 5V tolerant I/Os
- 0.18μm CMOS process
Applications
- PCI/CardBus WLAN adapter
- Wireless router
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